conditional PORT MAP in VHDL

Question

as i'm new to VHDL, it would be my pleasure to help me on this badboy. I am going to implement a logic that I don't know if it is possible or not. Assume that I want to instantiate 10 processors.

entity Processor is
    Port (
        Input : in integer;
        -- other ports
        );
end Processor;

architecture Behavioral of Processor is
    -- architecture implementation
begin
    -- processor logic here
end Behavioral;

My processor has an integer input that I must assign to a signal in the PORT MAP field But I want it to be conditional. If the condition is met, add 10 to the input of the signal processor. If the condition is not met, include signal 20.

ENTITY Interconnection_Network IS
END Interconnection_Network;

ARCHITECTURE Behavioral OF Interconnection_Network IS
    signal Condition : boolean := true;

    COMPONENT Processor IS

        PORT (
            
            input : IN INTEGER;
            -- other ports
        );
    END COMPONENT;


BEGIN

    Processor_Gen : FOR proc IN 0 TO 9 GENERATE
        Processor_Instance : Processor
       
        PORT MAP(
          if <condition> then
            input => 10;
        else
            input =>20;
        );
    END GENERATE Processor_Gen;
END Behavioral;

how can i do this?

these are not going to work

ENTITY Interconnection_Network IS
END Interconnection_Network;

ARCHITECTURE Behavioral OF Interconnection_Network IS
    signal Condition : boolean := true;

    COMPONENT Processor IS
        PORT (
            input : IN INTEGER
        );
    END COMPONENT;

BEGIN
    Processor_Gen : FOR proc IN 0 TO 5 GENERATE
        Processor_Instance : Processor
        PORT MAP(
            input => (IF Condition THEN 10 ELSE 20 END IF)
        );
    END GENERATE Processor_Gen;
END Behavioral;

or

ENTITY Interconnection_Network IS
END Interconnection_Network;

ARCHITECTURE Behavioral OF Interconnection_Network IS
    signal Condition : boolean := true;

    COMPONENT Processor IS
        PORT (
            input : IN INTEGER
        );
    END COMPONENT;

    signal InputValue : INTEGER;

BEGIN
    Processor_Gen : FOR proc IN 0 TO 5 GENERATE
        PROCESS
        BEGIN
            IF Condition THEN
                InputValue <= 10;
            ELSE
                InputValue <= 20;
            END IF;
        END PROCESS;

        Processor_Instance : Processor
        PORT MAP(
            input => InputValue
        );
    END GENERATE Processor_Gen;
END Behavioral;

Answer 1

In your last case, you need a unique signal for every generate - which can be done by declaring it in the generate declarative region:

ARCHITECTURE Behavioral OF Interconnection_Network IS
    signal Condition : boolean := true;

    COMPONENT Processor IS
        PORT (
            input : IN INTEGER
        );
    END COMPONENT;


BEGIN
    Processor_Gen : FOR proc IN 0 TO 5 GENERATE
         signal InputValue : INTEGER;
    BEGIN
        -- no need for a process here
        -- generate statements contain concurrent code like architectures
        InputValue <= 10 when Condition else 20 ; 

        Processor_Instance : Processor
        PORT MAP(
            input => InputValue
        );
    END GENERATE Processor_Gen;
END Behavioral;

Alternately since this is a constant value, you should probably do it as a generic rather than a port. Generics are constants and allow expressions on their inputs. While there is no VHDL syntax that can do this currently, you can call your own function, this would be:

ARCHITECTURE Behavioral OF Interconnection_Network IS
    signal Condition : boolean := true;

    COMPONENT Processor IS
        PORT (
            input : IN INTEGER
        );
    END COMPONENT;

    function IfElse(C : boolean; A, B : integer) return integer is
    begin
      if C then 
        return A ; 
      else
        return B ; 
      end if ; 
    end function IfElse ; 


BEGIN
    Processor_Gen : FOR proc IN 0 TO 5 GENERATE
    BEGIN
        Processor_Instance : Processor
        GENERIC MAP(
            input => IfElse(Condition, 10, 20) 
        )
        PORT MAP(
            ...
        );
    END GENERATE Processor_Gen;
END Behavioral;