Emacs Verilog 'compilation exited abnormally with code 255'

Question

module FullAdder (a, b, ci, r, co);
   input a, b, ci;
   output r, co;

   assign r = a ^ b ^ ci;
   assign co = (a&b) | ((a^b)&ci);

endmodule // FullAdder

module adder_4bit (A, B, ci, R, co);
   input [3:0] A, B; // [MSB:LSB]
   input       ci;
   output [3:0] R;
   output   co;
   wire [2:0]   c;
   
   // FullAdder i0 (.a(A[0]), .b(B[0]), .ci(ci), .r(R[0]), .co(c[0]));
   // FullAdder i1 (.a(A[1]), .b(B[1]), .ci(c[0]), .r(R[1]), .co(c[1]));
   // FullAdder i2 (.a(A[2]), .b(B[2]), .ci(c[1]), .r(R[2]), .co(c[2]));
   // FullAdder i3 (.a(A[3]), .b(B[3]), .ci(c[2]), .r(R[3]), .co(co));

   FullAdder i[3:0] (.a(A[3:0]), .b(B[3:0]), .ci({c[2:0],ci}), .r(R[3:0]), .co({co,c[2:0]}));

endmodule // adder_4bit

module adder_nbit (a, b, m, s, co, v);
   parameter N = 32; // 32 bit subtractor
   input [N-1:0] a, b;
   input     m;
   output [N-1:0] s;
   output    co, v;
   wire [N/4-1:0]     c;
   wire [N-1:0]       bi;

   genvar     i;

   assign bi[0] = b[0] ^ m;
   assign bi[1] = b[1] ^ m;
   assign bi[2] = b[2] ^ m;
   assign bi[3] = b[3] ^ m;

   adder_4bit add0(.A(a[3:0]), .B(bi[3:0]), .ci(m), .R(s[3:0]), .co(c[0]));

   generate
      for (i=1; i<=N/4-1; i=i+1) begin:bit
     assign bi[i*4] = b[i*4] ^ m;
     assign bi[i*4+1] = b[i*4+1] ^ m;
     assign bi[i*4+2] = b[i*4+2] ^ m;
     assign bi[i*4+3] = b[i*4+3] ^ m;
     adder_4bit add(.A(a[i*4+3:i*4]), .B(bi[i*4+3:i*4]), .ci(c[i-1]), .R(s[i*4+3:i*4]), .co(c[i]));
      end
   endgenerate

   assign co = c[N/4-1]; // carry
   assign v = c[N/4-2] ^ co; // overflow
endmodule // adder_nbit

`timescale 1ns/1ns
`include "FullAdder.v"
`include "adder_4bit.v"
`include "adder_nbit.v"

module subtractor_nbit_tb;
   parameter N = 32;
   reg [N-1:0] A, B;
   reg       M;
   wire [N-1:0] S;
   wire       CO, V;
   adder_nbit i0 (.a(A), .b(B), .m(M), .s(S), .co(CO), .v(V));

   initial
     begin
    $dumpfile ("subtractor_nbit_tb.vcd");
    $dumpvars(0, subtractor_nbit_tb);
    M=1; // subtractor
    A=0;
    B=0;

    #10 A=302;
    
    #10 B=100;
    
    #10 A=400;

    #10 B=203;

    #10 $finish;

     end // initial begin
endmodule // adder_4bit_tb

I'm making an n-bit subtractor with a 4-bit adder made with Fulladder. I put parameter N into n-bit subtractor. Depending on this N value, it was changed to 32, 36, or 40 bit subtracter.

When I run the simulation, 'compilation exited abnormally with code 255' error appears. What's wrong with the code?

I tried changing the xor method of b and m and changing the range of the for loop, but I keep getting the same error.

Answer 1

That error message is not very specific. If it is coming from emacs, then run the code directly on a simulator.

Since you are using iverilog, we can run it on EDA Playground. However, we still see a generic error message.

But, when run on the Cadence simulator, the error is much more meaningful:

     for (i=1; i<=N/4-1; i=i+1) begin:bit
                                        |
xmvlog: *E,FNDKWD (testbench.sv,47|40): A SystemVerilog keyword was found where an identifier was expected.

One way to fix this error is to change bit to another name, like bits. That allows the code to compile without errors.

---

The original code compiles cleanly if you disable SystemVerilog features in your simulator. For example, running iverilog without the -g2012 option. However, it is better to write code that compiles with SV features enabled.