I have a design which is verified functionally. I have generated bitstream for target "xc7z045." I set up debug to look at few internal signals. However, when i try to program, I am facing the following error:
ERROR: [Labtools 27-3412] Mismatch between the design programmed into the device 'xc7z045' (JTAG device index = '1' and the probes file(s) 'D:/Vivado_Workarea/rrc_filter/rrc_filter.runs/impl_1/TOP_ HDL_Wrapper.ltx'. The hw_probe 'ram_addr' in the probes file has port index '0'. This port location for the ILA core at location (uuid_23E7D65A79BC59F7BC47406C1714DFAE), does not support a data probe
I was able to program the device successfully when I removed the ILA probes.
This error is seen when there is a mismatch between a .bit file and .ltx file.
Sometimes changes made in the ILA are not reflected in the .ltx file, causing a mismatch between the .ltx and .bit file.
To work around the issue, please do the following:
Open the synthesized design. Use the following Tcl command: write_debug_probes -force filename.ltx Use the new .ltx file when programing the board.
See AMD/Xilinx Support #66860 or AMD/Xilinx another case for more on this.