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Generating verilog file for rocket chip

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#chisel #rocket-chip
59
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In chisel6.2.0, how to use hex file to init memory and test it?

Published on
#scala #sbt #chisel
37
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With Chisel How to avoid verilog file list at the end of generated file when using BlackBox?

Published on
#scala #verilog #chisel
39
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An error occured while testing Queue. 'FlitTypes' must be hardware, not a bare Chisel type

Published on
#chisel #chiseltest
42
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Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?

Published on
#scala #reduce #chisel
34
Views

How to propagate a value from a Module upwards

Published on
#scala #chisel
67
Views

Issues with creating an n-to-1 multiplexer in Chisel

Published on
#scala #chisel
39
Views

a chisel problem about some value only read-only

Published on
#scala #chisel
97
Views

Expecting a SInt value from a Wire, in Chisel

Published on
#scala #chisel #circuit #vlsi #chiseltest
165
Views

In FPGA, why counter with full adder raw implementation have better clock performance than infered addition '+'?

Published on
#fpga #chisel #yosys #icestorm
102
Views

How to implement the Gshare TAGE hybrid predictor combination on the RISC V BOOM core using Chisel

Published on
#scala #riscv #chisel #branch-prediction
35
Views

Variable sized type in Chisel

Published on
#chisel
85
Views

Adding a trivial bridge in FireSim

Published on
#scala #uart #chisel #bridge #rocket-chip
47
Views

Using Chisel Submodule within another Module: Cannot assign variables to the io input

Published on
#scala #hdl #chisel
41
Views

Use def or val in Chisle to define some "const-macro" value?

Published on
#chisel
124
Views

The problem with AyncFIFO with two clock sources written in Chisel 5.0

Published on
#chisel #chiseltest
111
Views

sbt test does not work and all the tests fail

Published on
#scala #ubuntu #fpga #chisel #rocket-chip
37
Views

How to export TileLink node to LazyModule's output and generate respective verilog file

Published on
#chisel #rocket-chip
359
Views

Type Casting in Chisel: Converting UInt to Int

Published on
#scala #error-handling #type-conversion #chisel #uint
109
Views

How is the SiFive interactive L2 cache connected to the Chipyard SoC?

Published on
#chisel #rocket-chip

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