DEVHIDE
Login Or Sign up

List Question

20
48
Views

Are FPGA GPIOs capable enough to read bits at a high rate (26Mbps)? If not, what is a possible way?

Published on
#emulation #fpga #gpio #xilinx #vlsi
51
Views

Shift and add binary multiplier getting don't-cares for reg2

Published on
#verilog #digital #vlsi
86
Views

NgSpice Installation

Published on
#linux #linux-kernel #vlsi #linuxthreads #ngspice
40
Views

Possible algo or approach to solve this type of floorplanning problem?

Published on
#algorithm #data-structures #cad #vlsi #polish-notation
32
Views

Why Ac_cdc01d rule in synopsis spyglass CDC is disabled by default?

Published on
#vlsi #system-clock #synopsys-vcs
23
Views

PRIMETIME | Issue linking hierarchal netlist

Published on
#vlsi #asic #physical-design
34
Views

The issue behind building a QuadTree

Published on
#python #data-structures #time-complexity #google-colaboratory #vlsi
39
Views

Find total number of instances of a module from rtl without using tool (python)

Published on
#python #module #register-transfer-level #vlsi
97
Views

Expecting a SInt value from a Wire, in Chisel

Published on
#scala #chisel #circuit #vlsi #chiseltest
132
Views

Convert lef-def layout to gds using klayout

Published on
#ruby #vlsi #stacklayout #docklayoutpanel
152
Views

Error in the code I am unable to solve it and i am unable to prevent the error

Published on
#verilog #system #vlsi
143
Views

Filter out pins having same clock attribute

Published on
#tcl #filtering #vlsi #cadence #searchfiltercollection
65
Views

Regarding "D0" drive strength cell

Published on
#vlsi
107
Views

STA of 2 clocks with the same frequency

Published on
#fpga #vlsi #asic
717
Views

what does Innovus dbGet command top.insts.cell.baseClass mean ? what are these values of top.insts.cell.baseClass mean?

Published on
#database #routes #tcl #vlsi
143
Views

"assign" followed by "always" - what is the order of evaluation?

Published on
#verilog #system-verilog #vlsi
276
Views

Does adding buffer in a digital path increase the delay or reduce the delay and why?

Published on
#digital #vlsi
1.7k
Views

how to declare integer variable in verilog to keep track of a value to be used in multiple for loops?

Published on
#verilog #vlsi
635
Views

Verilog [dot] meaning?

Published on
#verilog #vlsi
3.3k
Views

What is the difference between 2'b0 and 2'd0?

Published on
#verilog #system-verilog #register-transfer-level #vlsi

Trending Questions

Popular # Hahtags

javascript python java c# php android html jquery c++ css ios sql mysql r reactjs node.js arrays c asp.net json

Popular Questions

.

Copyright © 2021 Jogjafile Inc.