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20
53
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UVM agents - single/multiple?

Published on
#architecture #verification #uvm
58
Views

UVM RAL: NULL pointer is dereference

Published on
#verilog #system-verilog #verification #uvm
75
Views

Conditional creation of covergroup

Published on
#system-verilog #uvm
104
Views

Structure containing dynamic data in non-procedural context for parameterized test class

Published on
#system-verilog #uvm
104
Views

Can you use uvm_reg.get() on a volatile reg?

Published on
#system-verilog #uvm
187
Views

regexp in hdl path for UVM hdl access functions

Published on
#system-verilog #uvm #system-verilog-dpi
297
Views

Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

Published on
#system-verilog #uvm
82
Views

An abstract class cannot be instantiated in module

Published on
#class #module #system-verilog #new-operator #uvm
91
Views

Unexpected Queue Randomization with UVM environment

Published on
#oop #verilog #system-verilog #uvm
163
Views

Is it possible to create a uvm-test dynamically from a string pased via UVM_TESTNAME but then override the base-test with the newly crearted test?

Published on
#command-line-interface #system-verilog #uvm
532
Views

Is there any way to convert hierarchy as string to actual hierarchy

Published on
#system-verilog #uvm
127
Views

Constraint for square sub matrices in a matrix

Published on
#matrix #constraints #system-verilog #uvm
357
Views

I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

Published on
#system-verilog #verification #uvm #amba
112
Views

Multi-master AXI interface connections

Published on
#system-verilog #uvm #test-bench #amba
191
Views

Why uvm_hdl_force has effect only in interactive mode in Verdi?

Published on
#system-verilog #uvm
218
Views

If a single test case can not make the functional coverage get nearly 100%, is it acceptable to use several test cases to hit every point?

Published on
#system-verilog #verification #uvm #function-coverage
252
Views

How to write UVM driver and sequence item for a vending machine design (interview question)?

Published on
#system-verilog #verification #uvm
237
Views

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

Published on
#system-verilog #uvm
268
Views

Can an agent have many drivers, many monitors and many sequencers?

Published on
#uvm #test-bench
119
Views

What should I do to make the interface visible to some components?

Published on
#system-verilog #verification #uvm #questasim

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