How do I create a testbench for my Verilog code?

Question

I am trying to print the graph of this in Modelsim with Verilog

This is the code I wrote in Modelsim:

module circuit (
input A,
input B,
input C,
input D,
output reg F
);
always @* begin
F = ~(~A & B | B & ~C) | (A & ~D | B & D);
end
endmodule

I have to manually change A, B, C and D 16 times to simulate every possibility and print the graph. How do I create a testbench file so I can simulate the graph without manually changing values and pressing Run 16 times?

I tried writing this testbench.v file but it didn't work

module testbench;
    reg A, B, C, D;
    wire F;
    
    testbench TEST (
            .a(A),
            .b(B),
            .c(C),
            .d(D),
            .f(F)
        );

    initial begin
      
        A = 0; B = 0; C = 0; D = 0; #10;   
        A = 0; B = 0; C = 0; D = 1; #10;        
        A = 0; B = 0; C = 1; D = 0; #10;
        A = 0; B = 0; C = 1; D = 1; #10;

        A = 0; B = 1; C = 0; D = 0; #10;
        A = 0; B = 1; C = 0; D = 1; #10;
        A = 0; B = 1; C = 1; D = 0; #10;
        A = 0; B = 1; C = 1; D = 1; #10;

        A = 1; B = 0; C = 0; D = 0; #10;
        A = 1; B = 0; C = 0; D = 1; #10;
        A = 1; B = 0; C = 1; D = 0; #10;
        A = 1; B = 0; C = 1; D = 1; #10;

        A = 1; B = 1; C = 0; D = 0; #10;
        A = 1; B = 1; C = 0; D = 1; #10;
        A = 1; B = 1; C = 1; D = 0; #10;
        A = 1; B = 1; C = 1; D = 1; #10;
        
        $finish;
    end

endmodule

Answer 1

The testbench did not work because it has multiple issues. First issue in your testbench is that, you need to instantiate your circuit module but you have mistakenly instantiated the testbench itself that will cause the illegal recursive design instantiation error.

Secondly, you have instantiated the your module using the lowercase letters but your actual module ports are defined as uppercase ports. This will give you cannot find port 'a' on this module error. Know that Verilog is case sensitive, so you need to change the instantiation accordingly.

circuit TEST(
      .A(A),
      .B(B),
      .C(C),
      .D(D),
      .F(F)
);

How do I create a testbench file so I can simulate the graph without manually changing values and pressing Run 16 times?

In the testbench you have already provided all 16 combinations with a delay of #10, So you do not need to run it 16 times. You have to just run it once.