I am running a verilog file on Modelsim, however the wave area is empty and displays a "xxxxxx" message. I am very new to Verilog/Modelsim/Quartus in general, any help would be greatly appreciated! code:
module lfsr_prng (input clk,
rst,
output reg[2:0] out);
reg [5:0] lfsr;
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset the LFSR on rising edge of reset
lfsr <= 6'b000000;
end
else begin
// LFSR feedback logic
lfsr[5:1] <= lfsr[4:0];
lfsr[0] <= lfsr[5] ^ lfsr[4] ^ 1'b1;
// Assign output bits
out[2] <= lfsr[2];
out[1] <= lfsr[4];
out[0] <= lfsr[0];
end
end
endmodule
is it something with the output in my code that causes nothing to display on the wave area?
You need to run the simulation. do
run -ain the transcript window in modelsim