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20
33
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A FPGA Project Proposal where I can use both PS and PL

Published on
#embedded #fpga #vivado #hdmi #soc
50
Views

Is there a difference when using the ternary operator in always and assign statements?

Published on
#verilog #vivado
55
Views

IO placement is infeasible error in Vivado

Published on
#constraints #verilog #fpga #vivado
52
Views

Padding zeros with std_logic_vector results in Implementation Error

Published on
#vhdl #fpga #vivado
60
Views

always block not always triggering at event

Published on
#verilog #system-verilog #vivado
100
Views

How to write into 12 addresses at the same cycle in vivado and still be recognized as BRAM

Published on
#verilog #system-verilog #fpga #vivado
57
Views

VHDL Error - Washing Machine - unresolved signal is multiply driven

Published on
#vhdl #project #xilinx #vivado #vivado-hls
43
Views

Can SYSCLK be included in FPGA Xilinx vivado testbenches?

Published on
#fpga #clock #xilinx #vivado #test-bench
62
Views

How to resolve the following ILA probe error?

Published on
#debugging #hdl #vivado
51
Views

not showing the proper output

Published on
#verilog #system-verilog #fpga #vivado
45
Views

RISVC Single Cycle Processor Data Path and Testbench

Published on
#verilog #cpu-architecture #vivado
86
Views

xparameters.h not generating BRAM parameters

Published on
#vivado #vitis
101
Views

How to initialize coefficients of a large digital filter in Verilog?

Published on
#verilog #signal-processing #fpga #vivado #digital-design
87
Views

32-bit instructions memory in verilog

Published on
#memory #verilog #vivado
126
Views

Timing closure problems in FIFO

Published on
#verilog #timing #xilinx #fifo #vivado
91
Views

Simulation contradiction using the same Vivado block ram IP

Published on
#verilog #simulation #ram #vivado #test-bench
80
Views

VHDL Vivado: Can I make a variable std_logic_vector from separate std_logic inputs in the test bench?

Published on
#vhdl #vivado
98
Views

Xilinx Vivado schematic for if else statements

Published on
#if-statement #system-verilog #xilinx #vivado #synthesis
87
Views

FPGA Fancy flowing light, digital tube display?

Published on
#verilog #fpga #vivado
36
Views

How to get Vivado to properly respect recursive module instantiation?

Published on
#recursion #parameter-passing #verilog #vivado #iverilog

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