Russian peasant multiplication in VHDL

Question

I'm using Xilinx ISE to compile and simulate VHDL code. And I'm trying to compute the multiplication of two 8-bit numbers using the Russian algorithm. The following code is how I'm currently doing it:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity multiplier is
    port (
        multiplier : in STD_LOGIC_VECTOR(7 downto 0);
        multiplicand : in STD_LOGIC_VECTOR(7 downto 0);
        y : out STD_LOGIC_VECTOR(15 downto 0)
    );
end multiplier;

architecture Behavioral of multiplier is
begin
    process (multiplier, multiplicand)
        variable a : unsigned(7 downto 0) := unsigned(multiplier);
        variable b : unsigned(15 downto 0) := "00000000" & unsigned(multiplicand);
       variable c : unsigned(15 downto 0) := (others => '0');
    begin
        while a /= "00000001" loop
            a := a srl 1;
            b := b sll 1;
            if a(0) = '1' then
                c := c + b;
            end if;
        end loop;
        y <= STD_LOGIC_VECTOR(c);
    end process;
end Behavioral;

The Check Syntax button works fine but View RTL schematics fails to execute. Also when I try to simulate the code in the ISim software I get `The simulator has terminated in an unexpected manner. Please review the ISim log (isim.log) for details.

I've been trying to debug this code for half a day now and it seems like I'm working with user unfriendliest language on the user unfriendliest software.