use System Verilog $past in clocking gate

Question

p1: assert property (@(posedge clk) ($past(b, 2, c)) === 0);

when I run assert in VCS, it failed at 13s, 15s, 17s...

I don't know why it failed at 13s.

in 11s, $past(b, 2, c) is 0 (sampled at 7s)

but in 13s, c = 0, why $past(b, 2, c) get sampled value in 9s?

Answer 1

Using $past with an enable is complicated because it gates both the sampling and the history together. This of it as operating like this:

  always @(posedge clk) begin
    if(c) begin
      past1 <=b;
      past2 <= past1;
    end
    $display ("%t b:%0d b1:%0d b2:%0d", $time,b,past1,past2);
  end

BTW, it would really help to provide the exact stimulus in example code. A picture is nice, but trying to recreate it take a lot of people's time.

Answer 2

I suspect that it's failing because two clock cycles before 13 (i.e. 11), c was high, making the check valid, and b is 1- not 0 (as per the checker).