VHDL 8-bit unsigned counter overflow detection

Question

i am trying to create an 8-bit unsigned counter which count-step depends on the 3-bit control input. The problem is that the RST, control, addition, subtraction and underflow works correctly but overflow doesn't work at all. On the test bench when i get an overflow the overflow value itself doesn't seem to change from '0' to '1' as it should, but it just starts counting from the start.

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Counter is
    Port ( Clk : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           Control : in  STD_LOGIC_VECTOR (2 downto 0);
           Count : out  STD_LOGIC_VECTOR (7 downto 0);
           Overflow : out  STD_LOGIC;
           Underflow : out  STD_LOGIC;
           Valid : out  STD_LOGIC);
end Counter;

architecture Behavioral of Counter is
    signal tmpCount : UNSIGNED(7 downto 0) := (others => '0');
    signal tmpOverflow : STD_LOGIC := '0';
    signal tmpUnderflow : STD_LOGIC := '0';
    signal tmpValid : STD_LOGIC := '1'; 

begin

    process 
    begin
    

    wait until Clk'EVENT and Clk = '1';
    
    
    if tmpOverflow='1' or tmpUnderflow='1' or RST='1' then
        if RST='1' then 
            tmpCount<=(others=>'0');
            tmpOverflow<='0';
            tmpUnderflow<='0';
            tmpValid<='1';
        end if;
        
        else 
            if Control="000" then
                tmpCount<= tmpCount - 5;
            elsif Control="001" then
                tmpCount<=tmpCount - 2;
            elsif Control="011" then
                tmpCount<=tmpCount + 1;
            elsif Control="100" then
                tmpCount<=tmpCount + 2;
            elsif Control="101" then
                tmpCount<=tmpCount + 5;
            elsif Control="110" then
                tmpCount<=tmpCount + 6;
            elsif Control="111" then
                tmpCount<=tmpCount + 29;
        end if;
                
        if tmpCount > 255 then
            tmpOverflow <= '1';
        elsif tmpCount < 0 then
            tmpUnderflow <= '1';
        end if;

        end if;
        
        if tmpUnderflow='1' or tmpOverflow='1' then
            tmpValid<='0';
            tmpCount<= (others =>'U');
        end if;

    
    end process;
    
    Count<=std_logic_vector(tmpCount);
    Overflow<=tmpOverflow;
    Underflow<=tmpUnderflow;
    Valid<=tmpValid;

end Behavioral;