I'm learning risc-v instruction set. I know that "addi sp,sp,-40" will be converted to "fd810113". But I don't know why "addi sp,sp,-32" is converted to binary code "11 01".
Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?
419 Views Asked by Chris633 At
1
There are 1 best solutions below
Related Questions in ASSEMBLY
- Is there some way to use printf to print a horizontal list of decrementing hex digits in NASM assembly on Linux
- How to call a C language function from x86 assembly code?
- Binary Bomb Phase 2 - Decoding Assembly
- AVR Assembly Clock Cycle
- Understanding the differences between mov and lea instructions in x86 assembly
- ARM Assembly code is not executing in Vitis IDE
- Which version of ARM does the M1 chip run on?
- Why would %rbp not be equal to the value of %rsp, which is 0x28?
- Move immediate 8-bit value into RSI, RDI, RSP or RBP
- Unable to run get .exe file from assembly NASM
- DOSbox automatically freezes and crashes without any prompt warnings
- Load function written in amd64 assembly into memory and call it
- link.exe unresolved external symbol _mainCRTStartup
- x86 Wrote a boot loader that prints a message to the screen but the characters are completely different to what I expected
- running an imf file using dosbox in parallel to a game
Related Questions in RISCV
- How to change the gem5 RVV vector length
- Restoring division algorithm in Risc V
- RiscV checking if overflow has occurred during multiplication
- How can i get the vector register information in RVV0.7.1 when debugging with QEMU6.2?
- compile masstree from source in riscv64
- How to implement Combination and Permutation in RISC-V
- call a function from header file in C
- What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?
- What does madvise() do in virtual memory?
- How can I insert machine code into assembly language?
- Is it possible to manually change page table's PTE value? (xv6, risc-v,c)
- Differentiation of "Vector Load/Store Whole Register Instructions"
- Initializing array in RISC-V. How much space does it need?
- How do i create or edit basic, bmp image using risc-v assembler?
- How to run testbench.v with verilator
Related Questions in INSTRUCTION-ENCODING
- What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?
- x86_64 primary opcode byte categorization
- Breakdown MOV instruction on Intel 64 compatibility mode
- Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example
- How do I concatenate immediate value of type B RISC-V instruction?
- Are these push r16 encodings correct under 64BIT mode?
- Is the encoding "66| 48/ 0F 50 D8" in MASM for reg=rbx in "MOVMSKPD reg, xmm" correct?
- What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?
- Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?
- How is data width determined for load/store instructions in Rocket Core?
- Why does the opcode for MOV from a segment register not have its low bit set? It's not 8-bit operand-size, so the W bit should be set
- Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr
- Is "strb w0, [x2, w3, uxtw]" the same as "strb w0, [x2, w3, uxtw #0]"?
- Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?
- Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8
Trending Questions
- UIImageView Frame Doesn't Reflect Constraints
- Is it possible to use adb commands to click on a view by finding its ID?
- How to create a new web character symbol recognizable by html/javascript?
- Why isn't my CSS3 animation smooth in Google Chrome (but very smooth on other browsers)?
- Heap Gives Page Fault
- Connect ffmpeg to Visual Studio 2008
- Both Object- and ValueAnimator jumps when Duration is set above API LvL 24
- How to avoid default initialization of objects in std::vector?
- second argument of the command line arguments in a format other than char** argv or char* argv[]
- How to improve efficiency of algorithm which generates next lexicographic permutation?
- Navigating to the another actvity app getting crash in android
- How to read the particular message format in android and store in sqlite database?
- Resetting inventory status after order is cancelled
- Efficiently compute powers of X in SSE/AVX
- Insert into an external database using ajax and php : POST 500 (Internal Server Error)
Popular Questions
- How do I undo the most recent local commits in Git?
- How can I remove a specific item from an array in JavaScript?
- How do I delete a Git branch locally and remotely?
- Find all files containing a specific text (string) on Linux?
- How do I revert a Git repository to a previous commit?
- How do I create an HTML button that acts like a link?
- How do I check out a remote Git branch?
- How do I force "git pull" to overwrite local files?
- How do I list all files of a directory?
- How to check whether a string contains a substring in JavaScript?
- How do I redirect to another webpage?
- How can I iterate over rows in a Pandas DataFrame?
- How do I convert a String to an int in Java?
- Does Python have a string 'contains' substring method?
- How do I check if a string contains a specific word?
That is using the compressed instruction format:
C.ADDI[2:0] nzimm[5] dest[4:0] nzimm[4:0] C1[1:0]With
C.ADDIbeing000,SPbeing register #2 andC1being01it gives:000 1 00010 00000 01 = 0001 0001 0000 0001 = 0x1101Note that the compressed instruction only takes immediate from -32 to +31 due to having 6 bits of space which is why the other instruction with -40 is using the 32 bit format.