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List Question
20
Devhide
2024-03-26T07:36:05.720000
26
Views
What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?
Published on
26 March 2024 at 07:36
#qemu
#riscv
#instruction-encoding
93
Views
x86_64 primary opcode byte categorization
Published on
17 January 2024 at 13:47
#assembly
#x86-64
#intel
#disassembly
#instruction-encoding
130
Views
Breakdown MOV instruction on Intel 64 compatibility mode
Published on
04 December 2023 at 10:32
#assembly
#x86-64
#disassembly
#mov
#instruction-encoding
158
Views
Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example
Published on
29 November 2023 at 15:27
#assembly
#arm
#cortex-m
#thumb
#instruction-encoding
312
Views
How do I concatenate immediate value of type B RISC-V instruction?
Published on
10 October 2023 at 03:10
#assembly
#riscv
#instruction-encoding
#immediate-operand
63
Views
Are these push r16 encodings correct under 64BIT mode?
Published on
29 July 2023 at 10:33
#assembly
#x86-64
#intel
#machine-code
#instruction-encoding
165
Views
Is the encoding "66| 48/ 0F 50 D8" in MASM for reg=rbx in "MOVMSKPD reg, xmm" correct?
Published on
23 July 2023 at 09:27
#assembly
#x86-64
#masm
#avx
#instruction-encoding
119
Views
What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?
Published on
15 July 2023 at 04:44
#assembly
#x86
#x86-64
#avx512
#instruction-encoding
254
Views
Why does RISC-V 'J-immediate' encode imm[11] in inst[20]?
Published on
27 May 2023 at 13:42
#cpu-architecture
#riscv
#instruction-set
#instruction-encoding
44
Views
How is data width determined for load/store instructions in Rocket Core?
Published on
25 May 2023 at 17:51
#chisel
#rocket-chip
#instruction-encoding
257
Views
Why does the opcode for MOV from a segment register not have its low bit set? It's not 8-bit operand-size, so the W bit should be set
Published on
25 May 2023 at 11:40
#assembly
#x86
#cpu-architecture
#mov
#instruction-encoding
318
Views
Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr
Published on
24 April 2023 at 10:49
#assembly
#arm64
#instruction-set
#instruction-encoding
134
Views
Is "strb w0, [x2, w3, uxtw]" the same as "strb w0, [x2, w3, uxtw #0]"?
Published on
21 April 2023 at 06:08
#assembly
#arm64
#instructions
#addressing-mode
#instruction-encoding
419
Views
Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?
Published on
17 April 2023 at 13:46
#assembly
#riscv
#instruction-encoding
26
Views
Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8
Published on
25 February 2023 at 11:16
#assembly
#x86-64
#machine-code
#opcode
#instruction-encoding
72
Views
Jump addressing from PC to a target
Published on
21 February 2023 at 17:56
#assembly
#mips
#memory-address
#addressing
#instruction-encoding
216
Views
Convert assembly instruction set to16-bit numbers
Published on
31 January 2023 at 20:53
#assembly
#cpu-registers
#simulator
#instruction-encoding
258
Views
Opcode differences between MOV r/m32, imm32 and MOV r32, imm32
Published on
27 January 2023 at 22:25
#assembly
#x86-64
#machine-code
#opcode
#instruction-encoding
237
Views
getting an opcode? To perform jmp
Published on
15 January 2023 at 21:22
#assembly
#x86-64
#machine-code
#instruction-encoding
276
Views
Forcing a JMP rel32 (JMPQ)
Published on
12 December 2022 at 12:50
#assembly
#x86-64
#att
#instruction-encoding
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