Automatic syntax checking in Vivado doesn't work for testbenches?

Question

When I edit a VHDL testbench (simulation source) in Vivado (project mode), background syntax checking seems to be disabled: Obvious syntax errors like missing semicolons or undefined signals are not underlined with a squiggly red line (as in all design sources).

Is there a way to activate automatic background syntax checking for test benches? Could there be another reason why some files are not syntax-checked?

Answer 1

This seems to be missing feature: Xilinx Forums: No-syntax-highlighting-for-VHDL-testbenches