I have to use a multibit counter signal in another clock domain from the one that is generated. If there is no relation between the 2 clocks, is it safe to use gray code and classic 2 sync FFs and just read the coded value after that (just like it is done for pointers in asynchronous fifos)? In my understanding this would introduce less delay than using handshake signals ...
clock domain crossing of a mutli bit signal
647 Views Asked by user2609910 At
1
There are 1 best solutions below
Related Questions in SYNCHRONIZATION
- Can a D flip flop be enabled this way?
- Synchronous vs Asynchronous logic - SR-Flipflop
- Can using the ruby flip-flop as a filter be made less kludgy?
- Why does a Flip-Flop operator include the second condition?
- Can SystemVerilog represent a flip-flop with asynchronous set and reset without adding unsynthesizable code?
- Programming a ripple counter in C with JK flip flops
- Testbench for T Flip Flop using D Flip Flop in VHDL
- I'm struggling with writing the truth table for this state diagram for jk flip flops
- How to avoid red error lines (JK FlipFlop as subcircuit ) [Logisim]
- Quartus D Flip Flop with asynchronous reset
Related Questions in VHDL
- Can a D flip flop be enabled this way?
- Synchronous vs Asynchronous logic - SR-Flipflop
- Can using the ruby flip-flop as a filter be made less kludgy?
- Why does a Flip-Flop operator include the second condition?
- Can SystemVerilog represent a flip-flop with asynchronous set and reset without adding unsynthesizable code?
- Programming a ripple counter in C with JK flip flops
- Testbench for T Flip Flop using D Flip Flop in VHDL
- I'm struggling with writing the truth table for this state diagram for jk flip flops
- How to avoid red error lines (JK FlipFlop as subcircuit ) [Logisim]
- Quartus D Flip Flop with asynchronous reset
Related Questions in FPGA
- Can a D flip flop be enabled this way?
- Synchronous vs Asynchronous logic - SR-Flipflop
- Can using the ruby flip-flop as a filter be made less kludgy?
- Why does a Flip-Flop operator include the second condition?
- Can SystemVerilog represent a flip-flop with asynchronous set and reset without adding unsynthesizable code?
- Programming a ripple counter in C with JK flip flops
- Testbench for T Flip Flop using D Flip Flop in VHDL
- I'm struggling with writing the truth table for this state diagram for jk flip flops
- How to avoid red error lines (JK FlipFlop as subcircuit ) [Logisim]
- Quartus D Flip Flop with asynchronous reset
Related Questions in GRAY-CODE
- Can a D flip flop be enabled this way?
- Synchronous vs Asynchronous logic - SR-Flipflop
- Can using the ruby flip-flop as a filter be made less kludgy?
- Why does a Flip-Flop operator include the second condition?
- Can SystemVerilog represent a flip-flop with asynchronous set and reset without adding unsynthesizable code?
- Programming a ripple counter in C with JK flip flops
- Testbench for T Flip Flop using D Flip Flop in VHDL
- I'm struggling with writing the truth table for this state diagram for jk flip flops
- How to avoid red error lines (JK FlipFlop as subcircuit ) [Logisim]
- Quartus D Flip Flop with asynchronous reset
Related Questions in CLOCK-SYNCHRONIZATION
- Can a D flip flop be enabled this way?
- Synchronous vs Asynchronous logic - SR-Flipflop
- Can using the ruby flip-flop as a filter be made less kludgy?
- Why does a Flip-Flop operator include the second condition?
- Can SystemVerilog represent a flip-flop with asynchronous set and reset without adding unsynthesizable code?
- Programming a ripple counter in C with JK flip flops
- Testbench for T Flip Flop using D Flip Flop in VHDL
- I'm struggling with writing the truth table for this state diagram for jk flip flops
- How to avoid red error lines (JK FlipFlop as subcircuit ) [Logisim]
- Quartus D Flip Flop with asynchronous reset
Trending Questions
- UIImageView Frame Doesn't Reflect Constraints
- Is it possible to use adb commands to click on a view by finding its ID?
- How to create a new web character symbol recognizable by html/javascript?
- Why isn't my CSS3 animation smooth in Google Chrome (but very smooth on other browsers)?
- Heap Gives Page Fault
- Connect ffmpeg to Visual Studio 2008
- Both Object- and ValueAnimator jumps when Duration is set above API LvL 24
- How to avoid default initialization of objects in std::vector?
- second argument of the command line arguments in a format other than char** argv or char* argv[]
- How to improve efficiency of algorithm which generates next lexicographic permutation?
- Navigating to the another actvity app getting crash in android
- How to read the particular message format in android and store in sqlite database?
- Resetting inventory status after order is cancelled
- Efficiently compute powers of X in SSE/AVX
- Insert into an external database using ajax and php : POST 500 (Internal Server Error)
Popular # Hahtags
Popular Questions
- How do I undo the most recent local commits in Git?
- How can I remove a specific item from an array in JavaScript?
- How do I delete a Git branch locally and remotely?
- Find all files containing a specific text (string) on Linux?
- How do I revert a Git repository to a previous commit?
- How do I create an HTML button that acts like a link?
- How do I check out a remote Git branch?
- How do I force "git pull" to overwrite local files?
- How do I list all files of a directory?
- How to check whether a string contains a substring in JavaScript?
- How do I redirect to another webpage?
- How can I iterate over rows in a Pandas DataFrame?
- How do I convert a String to an int in Java?
- Does Python have a string 'contains' substring method?
- How do I check if a string contains a specific word?
Yes, using Gray encoding/decoding of the counter value over the Clock Domain Crossing (CDC) is the usual way to do it.
For this to work, the skew of the bits in the Gray encoded counter value plus the settling time for meta-stability must be less than the clock period. So remember to constrain the synthesis and Static Timing Analysis (STA).