Synthesize-able delay in Verilog

Question

I want to synthesize a SystemVerilog code that has delay written as ##1 but the synthesizer gives syntax errors as delay is not synthesize-able. I want to know is there any way I can give delay that will be synthesized? For instance, this is a SystemVerilog assertion in the code with delays

assert property ( ( req1 == 0 ) ##1( req1 == 1 ) ##1 !( req2 == 1 ) || ( gnt1 == 0 ) );

how can I synthesize this without losing its behavior?

Answer 1

Properties are not part of Verilog, but a part of SystemVerilog. More to the point, properties themselves are not synthesizable either. Properties are used in cover or assert statements in a simulation environment.

As for delays, your only option is to use a flip-flop to delay the signal. In your property ##1 means "on the next edge" assuming that your property has some clocking related to it (either in the cover/assert statement or that it is within a clocking-block).

To create synthesizable cycle-delays in otherwise synthesizable code:

always@(posedge ck or posedge arst) begin
  if(arst)
    data_delayed <= '0;
  else
    data_delayed <= data;
end  

Answer 2

The property you wrote does not make any sense. You cannot add delays in the middle of a Boolean expression. Did you mean to write a sequence of expressions instead? Then the correct syntax would be

sequence s1;
 ( ( req1 == 0 ) ##1( req1 == 1 ) ##1 !( req2 == 1 ) || ( gnt1 == 0 ) );
endsequence