I had two systems, let's say, system A and system B, so system A generates bits at the rate of 26Mbps from a physical pin, I need to capture/read all the data with system B which is ZC706 FPGA/any FPGA, I’m trying to read the bits through FPGA GPIOs, my doubt is, Are FPGA GPIOs capable enough to read bits at a high rate (26Mbps)? If not, what is a possible way?
I tried with ZC706 FPGA, i developed a system using with AXI GPIOs and developed a application software, to store the the data(bits). but the data mismatching beacuse of GPIO speeds. im unable to to solve this issue, any suggestions would be greatly appreciated.
Capturing megabits over a CPU-sampled interface (GPIO over AXI) is definitely not going to work at rates higher than maybe 5 MHz, and it's not the FPGA at fault here. Just imagine soft CPU at 100MHz, spending 4 clocks on each instruction, and you need at least 5 instructions to make a functional loop that captures the data - that already caps the speed at 100MHz/(4*5) = 5MHz
With FPGA you approach that task differently, you write the IP in the HDL of your choice, which samples the line at whatever frequency you want (like 200-400MHz), piles up the data into some ram block within the FPGA fabric, and then on some conditions (the trigger function, the buffer full, etc) signals the CPU that the data is received. The IP then continues to sample the data into another ram block, using both blocks in round-robin manner - one block is being accessed by CPU while the IP writes data into another block.