VHDL Repeat one number to std_logic_vector

Question

I'm new to VHDL and I'm trying to figure out a better way to accomplish the following. For example, I have one std_logic_vector of 2 bits called x and another std_logic_vector of 5 bits called y. I want to assign the first digit of x, which is x(0) to all 5 bits of y. I thought of doing y(0) <= x(0), y(1) <= x(0)... but it's not very convenient. Thanks for your time.

Answer 1

You can use this assignment:

    y <= (others => x(0));