Can synthesizers pay attention to intentional 'Z' at compile time?

Question

In Verilog, I have an input port that I would like to make optional. It's the start pin for a microarchitecture. If user does not want to drive the start pin manually, the module will use its own internal clock to drive the start pin.

It would be really nice if the user could hard code this pin to 'Z', and then the module has a snippet like this:

always @(posedge clk) begin 
  if (rst == 1'b1) begin 
    ...
  end else begin 
    if (start == 1'bz) begin 
      start_2 <= internally_generated_strobe;
    end else begin 
      start_2 <= start;
    end
  end
end

The port map to instantiate this module has something like this:

my_module INST_NAME (
  .clk(clk),
  .rst(rst),
  .start(1'bz),
  ...
  );

Is this something that most synthesizers support? Or will you get weird results?

I give this example in Verilog, but I'm also interested if VHDL vs. Verilog makes any difference.

Answer 1

There is no such thing as an X or Z state in real hardware, it is an abstract created by digital discrete simulation. In real hardware, a signal is has an analog voltage with a threshold that gets treated as a 0 or 1.

It's possible to create an analog circuit that could detect if a signal undriven, but no digital synthesis can do this.

What you can do is write a description that assigns a signal to an X state, and the synthesis tool will treat that as a "don't care" and create logic that assigns the signal to a 0 or 1 state; whichever state reduces the amount of hardware needed. A synthesis tool cannot create hardware that IS the X state nor can it create hardware that can detect an X state.

You can all write a description that assigns a signal to a Z state so that another assignment statement to the same signal can drive a 0 or 1 state. A synthesis tool will create hardware that turns off the driver to that signal, but the signal will eventually resolve to a 0 or 1 state depending on the presence of other active drivers on the signal, or the charge decay time of the wire.

For simulation debug, you can write a description that checks if a signal has been assigned the X or Z state using the identity operators === and !==, but no synthesis can create hardware that detects that because it does not exist in hardware. It will generate an error if you try.