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How do I diagnose and fix COMP96 ERROR COMP96_0055 and COMP96 ERROR COMP96_0056 when using Vunit to run my VHDL test bench

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#vhdl #active-hdl #vunit
84
Views

Natural number not overflowing in Aldec ActiveHdl

Published on
#vhdl #vivado #active-hdl
91
Views

Why do I get run time fatal error - Range width expression must be positive - for my up counter design?

Published on
#verilog #system-verilog #register-transfer-level #digital-design #active-hdl
34
Views

Error: COMP96_0207: Tarea_MUX_39203394.vhd : (53, 2): No actual specified for local port "SEL"

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#active-hdl
109
Views

Why are modules not connected to each other?

Published on
#verilog #active-hdl
630
Views

VHDL testbench code not showing output result of 1bit fulladder

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#vhdl #test-bench #active-hdl
1.5k
Views

I have the following errors appearing on my code, I don't know what they mean neither know how to fix them

Published on
#vhdl #active-hdl
4.5k
Views

Function to_hstring from std.textio is not working [VHDL]

Published on
#vhdl #active-hdl
438
Views

High impedance signal does not enter the test bench [VHDL]

Published on
#vhdl #waveform #active-hdl
165
Views

cocotb simulation with Aldec

Published on
#cocotb #active-hdl
2k
Views

Verilog and condition for Always block

Published on
#verilog #active-hdl
196
Views

Output array won't take the value of an array register

Published on
#verilog #active-hdl
976
Views

MachX03 library error in Active-hdl for fpga simulation

Published on
#vhdl #lattice-diamond #active-hdl
523
Views

My outputs in 4bits fullAdder are always z and don't change

Published on
#verilog #active-hdl
620
Views

Signal initialization VHDL

Published on
#vhdl #active-hdl
196
Views

PS2 Keyboard interface runs smoothly in Active-HDL simulator, but not working on Nexys2 Board

Published on
#vhdl #fpga #xilinx-ise #active-hdl
681
Views

How to find frequency of a clock divider ?

Published on
#vhdl #clock #active-hdl
136
Views

How can i solve bugs of my vhdl fifo memory?

Published on
#vhdl #fifo #active-hdl
1.2k
Views

Converting VHDL logic vectors to user-defined strings for simulation

Published on
#vhdl #fpga #lattice-diamond #active-hdl
466
Views

How to use microsoft visual studio as default text editor in Active-hdl

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#visual-studio-code #active-hdl

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