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101
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How to initialize coefficients of a large digital filter in Verilog?

Published on
#verilog #signal-processing #fpga #vivado #digital-design
65
Views

How can I avoid glitches in behavioural vhdl code simulations?

Published on
#vhdl #modelsim #digital #digital-design
184
Views

FIFO Depth Calculation

Published on
#fifo #soc #digital-design
99
Views

Function Wash not increasing value in sec signal in VHDL

Published on
#vhdl #fpga #quartus #digital-design
145
Views

1 bit comaparator using 2x1 mux ? Create First 1 bit magnitude comparator and implement on mux?

Published on
#bit #digital-design
91
Views

Why do I get run time fatal error - Range width expression must be positive - for my up counter design?

Published on
#verilog #system-verilog #register-transfer-level #digital-design #active-hdl
91
Views

how to add in binary

Published on
#binary #addition #digital-design
168
Views

Why do we have to add a "clr" (clean input wire) while forming a T flip-flop in Verilog with Vivado?

Published on
#verilog #system-verilog #vivado #flip-flop #digital-design
55
Views

Writing A'B'CD+ABC' using two inverters and 5 2:1 multiplexers

Published on
#logic #digital-design
418
Views

Continuous assignment with 0 delay not getting the expected value after a signal positive edge

Published on
#testing #system-verilog #digital-design
142
Views

What are buffers used for in the construction of the D latch?

Published on
#cpu-architecture #hardware #digital-design
647
Views

JK-Flip Flop: K-Map to find the Value of Next State (Qn+1)

Published on
#flip-flop #digital-design
621
Views

Verilog code is compiled but there is no "vcdplus.vpd" waveform file being created when using "$vcdpluson" - FSM Sequence Dectector

Published on
#verilog #state-machine #digital-design
425
Views

Problem while implementing JK-Flip Flop in VHDL

Published on
#vhdl #digital-logic #hardware #digital-design
83
Views

Programmable Logic Array (PLA) Design

Published on
#logic #digital-design
286
Views

How to create K-MAP from function

Published on
#digital-logic #digital-design
191
Views

applying stimulus to FPGA using PC

Published on
#fpga #vlsi #digital-design
213
Views

Can somebody explain the reasoning behind decimal to binary conversion?

Published on
#binary #digital-design
3.1k
Views

Asynchronous FIFO depth calculation

Published on
#fpga #asic #soc #digital-design
352
Views

Connecting Waveshare High-Precision AD/DA Board (ADS1256) to DE10-Nano Kit

Published on
#c #spi #intel-fpga #digital-design

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