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20
43
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Verilog module always going to default case when assigning value to input

Published on
#verilog #fpga #quartus #intel-fpga #questasim
19
Views

weird error happened when ran fpga program

Published on
#intel #fpga #intel-fpga #intel-oneapi #sycl
37
Views

Assistance Needed: Trouble Running Bare-Metal Code on second core in Cyclone V SoC

Published on
#arm #intel #bare-metal #intel-fpga #soc
32
Views

What is "strictly control signal" and Why is its input unconstrained?

Published on
#constraints #fpga #intel-fpga
65
Views

Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand

Published on
#verilog #quartus #intel-fpga
164
Views

How to add IP Libraries to Questa with Cocotb?

Published on
#intel-fpga #questasim #cocotb
112
Views

Fibonacci LFSR using the Altera Megafunction LPM_SHIFTREG - how to initialise? [VHDL]

Published on
#vhdl #fpga #intel-fpga #lfsr
108
Views

ModelSim Issue - Discrepancy of Data Output Results from ModelSim versus Altera's VWF Editor

Published on
#vhdl #modelsim #intel-fpga
161
Views

Analyzing synchronizer MTBF in Quartus

Published on
#verilog #fpga #quartus #intel-fpga
108
Views

Getting both lines to work on DE2-115 LCD screen

Published on
#verilog #intel-fpga
24
Views

dpcc code for fpga emulation using jupyter notebooks

Published on
#jupyter-notebook #jupyter-lab #hough-transform #intel-fpga #intel-oneapi
150
Views

How to read data from FPGA on HPS side

Published on
#fpga #intel-fpga
92
Views

Timing diagram of convst. signal of ADC (ads8556)

Published on
#adc #intel-fpga #texas-instruments
315
Views

Error: object on left-hand side of assignment must have a net type

Published on
#verilog #intel-fpga
232
Views

CLOCK_DEDICATED_ROUTE error in creating an RS latch

Published on
#vhdl #fpga #vivado #intel-fpga #flip-flop
90
Views

View report.html after DPC++ compilation for FPGA on DevCloud connected with Jupyter

Published on
#linux #intel-fpga #intel-oneapi #dpc++
714
Views

Output 'X' instead of '1' or '0' in VHDL

Published on
#vhdl #quartus #intel-fpga
85
Views

communication between PC and Altera through RS232 cable using VHDL and C#

Published on
#c# #serial-port #vhdl #communication #intel-fpga
348
Views

How to connect module to module in Verilog?

Published on
#verilog #system-verilog #fpga #quartus #intel-fpga
269
Views

How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus

Published on
#verilog #system-verilog #timing #quartus #intel-fpga

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