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Im trying to buil a “N” bit parameterizable accumulator based in an adder and in a register, both parameterizable

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#vhdl #quartus
43
Views

Verilog module always going to default case when assigning value to input

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#verilog #fpga #quartus #intel-fpga #questasim
78
Views

Failed to use memory bits in fpga

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#memory #verilog #fpga #ram #quartus
20
Views

Install SoC EDS and create .o file using Cygwin

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#cygwin #fpga #quartus #soc
99
Views

Why does running Synthesis take the same amount of time every time with Quartus, Vivado and Libero?

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#fpga #vivado #quartus #synthesis
65
Views

Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand

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#verilog #quartus #intel-fpga
124
Views

Compilation error in Quartus for Verilog language

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#verilog #system-verilog #quartus
143
Views

Produce sine lookup table based on the frequency

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#vhdl #trigonometry #fpga #quartus #sine-wave
66
Views

Why is Modelsim displaying "Error: MIF contains illegal character" when I try to simulate?

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#simulation #modelsim #quartus
172
Views

Questa Error "UI-Msg: (vish-4014) No objects found matching " while running from quartus

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#vhdl #quartus #questasim
58
Views

I kept getting the error “ Case statement must cover all possible values of expression”. How do I fix this?

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#vhdl #quartus
161
Views

Analyzing synchronizer MTBF in Quartus

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#verilog #fpga #quartus #intel-fpga
69
Views

Control signal with two buttons

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#vhdl #quartus
147
Views

When I simulate my counter in Modelsim, the outputs are undefined

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#verilog #modelsim #quartus
65
Views

Using a macro gives errors, but putting macro text in explicitly does work

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#verilog #system-verilog #quartus
36
Views

How to convert a wav file into a data array and upload it to intel quartus?

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#quartus
122
Views

Assign a Output into Two Modules in Verilog

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#verilog #system-verilog #fpga #hdl #quartus
211
Views

VHDL Ping Pong Game on Cyclone IV EP4CE22 - Display Not Updating Correctly

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#vhdl #fpga #modelsim #quartus
147
Views

Why do I get "object std is not declared" error when I use std::randomize?

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#system-verilog #quartus #test-bench
99
Views

Function Wash not increasing value in sec signal in VHDL

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#vhdl #fpga #quartus #digital-design

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