Assign a Output into Two Modules in Verilog

Question

In the below Verilog Code, I want to assign my outputs into two modules namely two_input_checker and three_input_checker. But when I assigned them directly as shown as below, it gives a error.

module logical_function_check (
  IN1, IN2, IN3, IN4, IN5, IN6, 
  IN8, IN9, IN10, IN11, IN12, IN13,
  OP1, OP2, OP3, OP4, OP5, OP6,
  OP8, OP9, OP10, OP11, OP12, OP13,
  pass1, pass2, pass3, pass4, pass5, pass6,
  fail1, fail2, fail3, fail4, fail5, fail6,
  pass, fail,
  clk
);
  
  input OP1, OP2, OP3, OP4, OP5, OP6, OP8, OP9, OP10, OP11, OP12, OP13;
  output IN1, IN2, IN3, IN4, IN5, IN6, IN8, IN9, IN10, IN11, IN12, IN13;
  output pass1, pass2, pass3, pass4, pass5, pass6, fail1, fail2, fail3, fail4, fail5, fail6;
  output pass, fail;
  input clk;
  

  two_input_checker two_input_checker_inst(
    .A1(IN1),
    .A2(IN4),
     .A3(IN10),
     .A4(IN13),
     .B1(IN2),
     .B2(IN5),
     .B3(IN9),
     .B4(IN12),
    .op1(OP3),
    .op2(OP6),
    .op3(OP8),
    .op4(OP11),
    .pass1(pass1),
    .pass2(pass2),
    .pass3(pass3),
    .pass4(pass4),
    .fail1(fail1),
    .fail2(fail2),
    .fail3(fail3),
    .fail4(fail4),
    .pass(pass),
    .fail(fail),
     .clk(clk),
     .enable(1'b1)
  );
  
  three_input_checker three_input_checker_inst (
    .A1(IN1), 
    .A2(IN3), 
    .A3(IN11), 
    .B1(IN2), 
    .B2(IN4), 
    .B3(IN10),
    .C1(IN13), 
    .C2(IN5), 
    .C3(IN9),
    .op1(OP12), 
    .op2(OP6), 
    .op3(OP8),
    .pass1(pass1), 
    .pass2(pass2), 
     .pass3(pass3),
    .fail1(fail1), 
     .fail2(fail2), 
     .fail3(fail3),
    .pass(pass), 
     .fail(fail),
    .clk(clk),
     .enable(1'b0)
  );
    

endmodule

The error is shown below.

enter image description here

How can I fix that error and assign the outputs? Or are there any other method to do that?

Answer 1

I am assuming here that you are assigning one signal to two output ports. You need to use different signals for the two modules' outputs and then OR these signals. Signals cannot be driven from multiple drivers. Example for signal pass1:

pass1 = two_input_checker_inst_pass1 | three_input_checker_inst_pass1;

Answer 2

The error indicates that you have muti driven nets.

Let's take for example your output "pass1" - it's driven once from two_inputs_checker.pass1 output port, and once from three_inputs_checker.pass1 output port. What you are trying to do is not allowed in synthesizable HDL.

For what you are doing - a net can have only a single driver.

Same goes for all the nets in the image you gave. Notice for example, that you don't get this error for IN3, which is driven only by three_input_checker.A2 output port.

What you can do is one of the next, which all depends on what you want to do and what is the behavior you want from your RTL:

Add more output ports:

For example, pass1 can be duplicated to pass1_0 and pass1_1, or more cleanly, can be changed to:

output [1:0] pass1;

Then you can connect two_inputs_checker to pass1[0] and three_inputs_checker to pass1[1].

Obviously, someone needs to do something with two outputs instead of only one output.

Define some internal boolean logic between the colliding drivers:

Again, let's take pass 1 as an example. You can maybe say that it makes sense to define that pass1 should be set only if the two checkers say that they got pass1. i.e.:

pass1 = three_inputs_checker.pass1 AND two_inputs_checker.pass1

You can specify this logic using RTL coding. You add internal wires:

wire two_inputs_pass1;

wire three_inputs_pass1;

You connect two_inputs_pass1 to two_inputs_checker. You connect three_inputs_pass1 to three_inputs_checker.

then you assign:

assign pass1 = two_inputs_pass1 | three_inputs_pass1;

Remove one of the drivers:

Maybe you don't need all the outputs from the two units. For example, perhaps it's enough to use just IN1 that comes from two_inputs_checker, so you can leave the three_inputs_checker.A1 unconnected:

three_input_checker three_input_checker_inst (
.A1(),
 ...