Dump all values of input outputs of submodule in vhdl project

Question

I have build a cpu in vhdl. The cpu contains alu, ram, mux and other submodules. Now I want to dump all the values of inputs and outputs of submodules into csv or vcd files. I want to observe the changes for suppose 20 clock cycle. How can I do it in VHDL. I am using ModelSim for simulation.

Thanks in advance.

Answer 1

Open a List Window in modelsim. Add the signals you want to dump. Run the sim.
File -> Write List -> Tabular.