System Verilog - How to only take the top half of the bits from the result of a signed integer product

Question

I am programming a basic ALU in system verilog. The ALU takes inputs from the 16 bit registers InDest and InSrc and outputs the result to the 16 bit register OutDest. One of the required instructions is MUH, which sets the value of register OutDest to the high half of the signed integer product InDest*InSrc.

For instance, if the result of the multiplication is:

1111 1111 1111 1111 0000 0000 0000 0000

The value of OutDest should be:

1111 1111 1111 1111

The use of other registers is not allowed.

My initial idea for this instruction was:

{OutDest,null} = {(InSrc*InDest)};

However this gives the error: near text: "null"; expecting "}".

I have also tried:

OutDest = {InSrc*InDest}[31:16];

This gives the error: near text : "["; expecting ";".

Any help on this instruction would be greatly appreciated, since alot of time has been spent on it and it is a important piece of coursework.

Answer 1

module tb ();
  
  logic signed [7:0]  rhs1,rhs2;
  logic signed [15:0] product;
  
  initial
    begin
      // 8 bits * 8 bits = 16 bits
      rhs1 = -1;
      rhs2 = 1;
      product = rhs1 * rhs2;
      // take the top half of the vector
      $display("lsh = %0h",product[15:8]);
    end
  
endmodule

Produces:

lsh = ff

Answer 2

This is the correct syntax

OutDest = {(32'InSrc*InDest)}[31:16];

But it seems your version of Quartus is not supporting it.

You could write

OutDest = 32'(InSrc*InDest) >> 16;