Question

Freeze after two subsequent software resets for Zynq 7000 FPGA (with SoC)

score 14 · Answer 1 · 2024-03-19T13:45:17.113000

14

Views

Freeze after two subsequent software resets for Zynq 7000 FPGA (with SoC)

Published on 19 March 2024 at 13:45

score 38 · Answer 2 · 2024-03-12T15:51:38.577000

38

Views

embedded linux buildroot how to work with axi-gpio?

Published on 12 March 2024 at 15:51

score 11 · Answer 3 · 2024-03-12T14:03:35.483000

11

Views

BUG in HDMI showing black screen in frame difference experiment on ZYNQ platform

Published on 12 March 2024 at 14:03

score 49 · Answer 4 · 2024-03-12T09:32:16.947000

49

Views

buildroot for zedboard, how to enable axi-gpio in device tree?

Published on 12 March 2024 at 09:32

score 21 · Answer 5 · 2024-03-08T20:02:07.370000

21

Views

Can we increase interrupt number from command prompt?

Published on 08 March 2024 at 20:02

score 61 · Answer 6 · 2024-02-29T11:54:13.150000

61

Views

Zynq UltraScale+ zcu3eg - coresight trace

Published on 29 February 2024 at 11:54

score 77 · Answer 7 · 2024-02-28T21:58:44.893000

77

Views

Why interrupts are not shown in /proc/interrupts?

Published on 28 February 2024 at 21:58

score 118 · Answer 8 · 2024-02-08T20:44:12.080000

118

Views

Why I cannot write to registers of my zynq board?

Published on 08 February 2024 at 20:44

score 86 · Answer 9 · 2024-01-25T14:58:06.397000

86

Views

How to trigger a software generated interrupt on core1 from core1 on bare metal?

Published on 25 January 2024 at 14:58

score 205 · Answer 10 · 2023-11-30T23:14:20.330000

205

Views

Under what condition I can "write" but cannot "read" from a location?

Published on 30 November 2023 at 23:14

score 117 · Answer 11 · 2023-11-15T10:17:08.603000

117

Views

Is it possible to overload the DDR controller on Zynq through PL ? An how to analyze it?

Published on 15 November 2023 at 10:17

score 86 · Answer 12 · 2023-11-08T12:36:56.847000

86

Views

How can I ensure that if petalinux has configured oled drivers for me

Published on 08 November 2023 at 12:36

score 357 · Answer 13 · 2023-10-27T19:16:43.610000

357

Views

can't access /dev/mem in a docker container

Published on 27 October 2023 at 19:16

score 352 · Answer 14 · 2023-10-24T03:21:21.093000

352

Views

How to check if interrupts are working or not?

Published on 24 October 2023 at 03:21

score 17 · Answer 15 · 2023-10-01T14:10:27.943000

17

Views

How to generate inter cortexA9 interrupts based on internal timers

Published on 01 October 2023 at 14:10

score 178 · Answer 16 · 2023-09-22T06:32:56.990000

178

Views

Datasheet says EEPROM address is 0xA0 but it worked for me on 0x50. Is there a particular reason to right-shift bits?

Published on 22 September 2023 at 06:32

score 57 · Answer 17 · 2023-09-07T06:23:05.473000

57

Views

What data type should use in software of fft vivado?

Published on 07 September 2023 at 06:23

score 99 · Answer 18 · 2023-09-07T04:57:45.000000

99

Views

Reading AXSS (USR_ACCESS) register on a Xilinx Zynq-7000 Petalinux with FPGA Manager | No such file or directory error

Published on 07 September 2023 at 04:57

score 116 · Answer 19 · 2023-08-14T21:44:50.360000

116

Views

ZYNQ board doesn't recognized usb flash drive

Published on 14 August 2023 at 21:44

score 217 · Answer 20 · 2023-07-28T09:56:47.460000

217

Views

Vivado won't synthesize BRAM, making LUT instead

Published on 28 July 2023 at 09:56

List Question

Freeze after two subsequent software resets for Zynq 7000 FPGA (with SoC)

embedded linux buildroot how to work with axi-gpio?

BUG in HDMI showing black screen in frame difference experiment on ZYNQ platform

buildroot for zedboard, how to enable axi-gpio in device tree?

Can we increase interrupt number from command prompt?

Zynq UltraScale+ zcu3eg - coresight trace

Why interrupts are not shown in /proc/interrupts?

Why I cannot write to registers of my zynq board?

How to trigger a software generated interrupt on core1 from core1 on bare metal?

Under what condition I can "write" but cannot "read" from a location?

Is it possible to overload the DDR controller on Zynq through PL ? An how to analyze it?

How can I ensure that if petalinux has configured oled drivers for me

can't access /dev/mem in a docker container

How to check if interrupts are working or not?

How to generate inter cortexA9 interrupts based on internal timers

Datasheet says EEPROM address is 0xA0 but it worked for me on 0x50. Is there a particular reason to right-shift bits?

What data type should use in software of fft vivado?

Reading AXSS (USR_ACCESS) register on a Xilinx Zynq-7000 Petalinux with FPGA Manager | No such file or directory error

ZYNQ board doesn't recognized usb flash drive

Vivado won't synthesize BRAM, making LUT instead

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