How to syntax check VHDL in Vivado without complete synthesis

Question

What's the simplest way to syntax-check my VHDL in Vivado without running through a full synthesis?

Sometimes I code many inter-related modules at once, and would like to quickly find naming errors, missing semi-colons, port omissions, etc. The advice I've read is to run synthesis, but that takes longer than I need for just a syntax check. I've observed that syntax errors will usually cause synthesis to abort within the first minute or so, so my workaround is to run synthesis and abort it manually after about a minute.

Answer 1

In the Vivado Tcl Console window, the check_syntax command performs a fast syntax check, catches typos, missing semi-colons, etc.

Answer 2

Vivado offers an elaboration step before synthesis. This is the lightweight version of y synthesis by just reading all sources and creating a design model based on the language without optimizations and transformations.

A pure syntax check per file is not enough in many cases. You also want to know if certain identifiers exist and if types are matching. Therefore, an elaboration is needed.

(If you never have heard of that step: VHDL compiling has 2 steps: Analysis and Elaboration. Think of elaboration like of linking in ANSI C.)