I am trying to declare a Package to add 2 4-bit STD_LOGIC_VECTOR and return a 4-bit STD_LOGIC_VECTOR Result and 1-bit Carry

Question

I an using Xilinx ISE Tool for it.

STEPS FOLLOWED:-

1. Created a Project in Xilinx ISE.
2. Added VHDL Package as a Source.
3. Wrote Code to declare the Package to add two 4-bit STD_LOGIC_VECTORs and return a 4-bit STD_LOGIC_VECTOR Result and a 1-bit STD_LOGIC Carry.
4. Added another New Source (VHDL Module) to the Project to simply write Code to see if my package works fine.
5. Wrote a Test-bench to Verify the DUT by adding another New Source (VHDL Test Bench) to the DUT.

When I checks Behavioral Check Syntax for the TB, it compiled with 2 WARNINGS:

WARNING 1:- Line 39: Subprogram <"+"> does not conform with its declaration. WARNING 2:- Line 39: Function "+" does not always return a value.

I Simulated (using Simulate Behavioral Model) the TB anyway, but NO WAVEFORM IS BEING SHOWN.

Please guide me to resolve this.

VHDL PACKAGE:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package my_package is

function "+" (a,b : std_logic_vector)
return std_logic_vector;

end package my_package;

package body my_package is

function "+" (a,b : std_logic_vector(3 downto 0))
return std_logic_vector is
    
variable result : std_logic_vector (3 downto 0) := "0000";
variable carry : std_logic := '0';

begin

for i in a'reverse_range loop
result(i) := a(i) xor b(i) xor carry;
carry := (a(i) and b(i)) or (b(i) and carry) or (a(i) and carry);
end loop;
end "+";

end package body my_package;

VHDL MODULE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.my_package.all;

entity my_package_check is
Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
B : in  STD_LOGIC_VECTOR (3 downto 0);
C : in  STD_LOGIC;
res : out  STD_LOGIC_VECTOR (3 downto 0);
Cout : out  STD_LOGIC);
end my_package_check;

architecture Behavioral of my_package_check is
SIGNAL Z : STD_LOGIC_VECTOR (4 downto 0);
begin
Z <= A + B;
res <= Z (3 downto 0);
Cout <= Z(4);
end Behavioral;

VHDL TEST BENCH:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY my_package_checktb IS
END my_package_checktb;

ARCHITECTURE behavior OF my_package_checktb IS 

COMPONENT my_package_check
PORT(
C : IN std_logic;
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
res : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;

SIGNAL C :  std_logic :='0';
SIGNAL A :  std_logic_vector(3 downto 0) := "0000";
SIGNAL B :  std_logic_vector(3 downto 0) := "0000";
             
SIGNAL Cout :  std_logic;
SIGNAL res :  std_logic_vector(3 downto 0);
          

BEGIN

uut: my_package_check PORT MAP(
A => A,
B => B,
C => C,
res => res,
Cout => Cout
);

A <= "0000", "1111" after 100 ns;
B <= "0000", "1111" after 100 ns;

END;

NOTE:- AS PROVIDENG TEST VECTORS FOR INPUTS via STIMULUS PROCEESS, was throwing in ERROS, I used a different Method to provide the Test Vectors.

AIM:- To get the Output Waveform and verify the functionality of the "+" Function declared in Package.

Answer 1

Your custom "+" function does not have a return statement. It needs to end with:

Return carry & result;

Note: Vhdl already has arithmetic functions in the numeric_std package